December 16, 2019 -- Mentor, a Siemens business, today announced that leading artificial intelligence (AI) solution provider Enflame Technology recently used Mentor’s Tessent™ software product family to successfully meet silicon test requirements and achieve rapid test bring-up for its new Deep Thinking Unit (DTU) chip.
Introduced earlier this week, Enflame’s DTU chip targets deep learning training in datacenters. The chip helps lower the cost of accelerating AI applications in cloud and enterprise datacenters, while helping deliver exceptional performance for training tasks.
Based in Shanghai, China, Enflame develops deep learning software stacks and accelerator system-on-chips (SoCs) to deliver AI training platform solutions for the global datacenter and cloud service provider markets.
“Tessent tools help enable faster DFT development and debugging turnaround cycles between design, verification and physical design, which is essential for large AI chips as they continue to grow in size,” said Iris Ma, SoC DFX director at Enflame Technology. “The register-transfer level-based hierarchical design-for-test capabilities within Tessent offer an ideal solution for implementing DFT and automatic test pattern generation, not only in our huge current-generation devices, but also for our next-generation chip, which is even bigger.”
When developing its new DTU chip, Enflame required a DFT solution that minimized test cost, reduced defective parts-per-million (DPPM) and accelerated time to market. Making these requirements especially challenging was the exceptionally large size of the chip’s design, which integrates more than 10 billion transistors, incorporates high bandwidth memory (HBM)2 with 2.5D package and is manufactured at 12nm.
"Mentor’s Tessent DFT and Calibre physical verification tools played a critical role in the development of our new DTU AI chip, which includes 480mm2 prime die and HBM2 with 2.5D package,” said Arthur Zhang, COO of Enflame Technology. “We are thrilled to say that we rapidly achieved bring-up, with the ASIC back to us in seven days. All DC/AC scan, memory BIST, boundary scan and analog tests completed with zero issues. In addition, all wafer-sort/FT/SLT are automated and initial yield is aligned with foundry index. The wafer-sort, FT, SLT and lab results correlated properly. We sincerely thank Mentor for its outstanding tool quality, exceptional innovation and constant support.”
Mentor’s Tessent software is a market-leading DFT solution, helping companies achieve higher test quality, lower test cost and faster yield ramps. The register-transfer level (RTL)-based hierarchical DFT Tessent with Tessent Connect automation features an array of technologies specifically suited to address the DFT implementation and pattern generation challenges of AI chip architectures. These technologies help to avoid DFT considerations from presenting delays to aggressive production schedules, which are common in emerging markets such as AI processing.
“Hardware acceleration for AI is now a very competitive and rapidly evolving market. As a result, fast time to market is a leading concern for many of our customers in this segment,” said Brady Benware, VP and GM for the Tessent product family at Mentor, a Siemens business. “Companies participating in this market are choosing Tessent because of its advanced hierarchical DFT approach and Tessent Connect automation, which together provide extremely efficient test implementation for massively parallel architectures. In addition, SiliconInsight debug and characterization capabilities in Tessent help eliminate costly delays during silicon bring-up.”
To learn more about Tessent solutions for AI accelerators, please visit https://bit.ly/2DPY9ZO. To learn more about Tessent Connect automation, please visit https://bit.ly/388Z6ta.
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